AArch64 MP+dmb.sy+addr-[fr-dmb.st-rf]-addr
"DMB.SYdWW Rfe DpAddrdR FrLeave DMB.STdWW RfBack DpAddrdR Fre"
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T,2:z=F,2:a=W
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe DpAddrdR FrLeave DMB.STdWW RfBack DpAddrdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X4=z; 1:X6=a; 1:X9=x;
2:X1=z; 2:X3=a;
}
P0 | P1 | P2 ;
MOV W0,#1 | LDR W0,[X1] | MOV W0,#1 ;
STR W0,[X1] | EOR W2,W0,W0 | STR W0,[X1] ;
DMB SY | LDR W3,[X4,W2,SXTW] | DMB ST ;
MOV W2,#1 | LDR W5,[X6] | MOV W2,#1 ;
STR W2,[X3] | EOR W7,W5,W5 | STR W2,[X3] ;
| LDR W8,[X9,W7,SXTW] | ;
exists
(1:X0=1 /\ 1:X3=0 /\ 1:X5=1 /\ 1:X8=0)